library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity zx128e is port( res: in std_logic:='1'; -- ????? --clock: in std_logic; -- 28 Mhz clock clock56: in std_logic; -- 56 Mhz clock clock_cpu: out std_logic; -- 3,5 Mhz CPU clock clock_mmc: out std_logic; adr0:in std_logic; adr1:in std_logic; adr: in std_logic_vector(13 downto 2); -- ????? ???????? adr14:in std_logic; adr15:in std_logic; addr_video: out std_logic_vector(15 downto 0); -- ????? ???????? adr_rom: out std_logic_vector(2 downto 0); adr_rom128:out std_logic; adr14m:out std_logic; adr15m:out std_logic; adr16m:out std_logic; data_cpu: inout std_logic_vector(7 downto 0) := "ZZZZZZZZ"; -- ?????? ?? CPU data_video: inout std_logic_vector(7 downto 0) := "ZZZZZZZZ"; --?????? ??? ??? ???????? 0 ka: out std_logic_vector(2 downto 0); jk: in std_logic_vector(5 downto 0); m1: in std_logic; rd: in std_logic:='1'; -- read wr: in std_logic:='1'; -- write mreq: in std_logic:='1'; -- ?????? iorq: in std_logic:='1'; --???? mem_r: out std_logic; -- read memory mem_w: out std_logic; -- write memory r0: out std_logic; -- read memory w0: out std_logic; -- write memory cs_rom: out std_logic :='1'; cs_ram1: out std_logic :='1'; cs_fe: out std_logic :='1'; bc1:out std_logic; bdir:out std_logic; sound: out std_logic; --tipe_in:in std_logic; csmmc: out std_logic; rd_mmc: out std_logic; wr_mmc: out std_logic; rgby: out std_logic_vector(3 downto 0); -- red,green,blue colors & ??????? int: out std_logic; sync: out std_logic ); end zx128e; architecture zx128e_arch of zx128e is signal clock: std_logic; -- 28 Mhz clock signal del: std_logic_vector(1 downto 0); signal del_mmc: std_logic_vector(1 downto 0); signal hcnt_del: std_logic_vector(8 downto 0); -- ???????-???????? ?? 2 ? 4,??????? ???????? ?? ??????????? signal vcnt: std_logic_vector(8 downto 0); --??????? ???????????? ????? signal fl_del: std_logic_vector(4 downto 0); signal fe_rg: std_logic_vector(4 downto 0); -- порт #FE signal fd_rg: std_logic_vector(5 downto 0); --порт #FD signal blank: std_logic; -- video blanking signal signal pixrg: std_logic_vector(7 downto 0); -- регистр пикселей signal tilrg: std_logic_vector(7 downto 0); -- рогистр тайла signal io_w: std_logic; --------------------------------------------------------------------- signal ale: std_logic; signal ale_tile: std_logic; signal pixw: std_logic; signal bord: std_logic; --------------------------------------------------------------------- signal hsync: std_logic; --?????????????? ????????????? signal vsync: std_logic; --???????????? ????????????? signal pixw1: std_logic; signal tilw: std_logic; signal flash: std_logic:='0'; signal adr_ram_ext: std_logic_vector(2 downto 0); signal strt: std_logic:='1'; signal stp: std_logic:='1'; begin