PENTAGON 1024 - disable 1MB

Please test this basic program on real PENTAGON 1024SL (with 48rom)

1 CLEAR 49151:OUT 61431,0
2 OUT 32765,16:POKE 49152,16
3 OUT 32765,80:POKE 49152,80
4 OUT 61431,4:PRINT PEEK 49152
5 OUT 61431,0:PRINT PEEK 49152

After run will program show 80 + 80

After set bit D2=1 will only ignored D5,D6,D7 on port 7FFD and disabled memory 1MB ? :v2_eek:

I enable 1MB ram and set on port 7FFD bits D7 via OUT 32765,128+16. After disable 1MB memory via OUT EFF7,4 is (in UNREALSPECCY emulator) from adress 49152 same page from 1MB extra memory. But this memory is disabled. It's correct ?

Цитата:

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Сообщение от VELESOFT

After set bit D2=1 will only ignored D5,D6,D7 on port 7FFD or will reset bits D5,D6,D7 on port 7FFD and disabled memory 1MB ?

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The internal state of the port #7FFD is not changed, address line A17', A18', A19' will be set to zero.

---------- Post added at 01:14 ---------- Previous post was at 01:09 ----------

Цитата:

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Сообщение от VELESOFT

I enable 1MB ram and set on port 7FFD bits D7,D6,D5. After disable and enable 1MB memory via OUT EFF7,4 + OUT EFF7,0 will in UNREALSPECCY emulator reset bits D7,D6 and D5 on paging port 7FFD. It's correct ?

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This is wrong. The internal state of the port #7FFD not change.

Цитата:

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Сообщение от БК-0010

The internal state of the port #7FFD is not changed, address line A17', A18', A19' will be set to zero.

---------- Post added at 01:14 ---------- Previous post was at 01:09 ----------

This is wrong. The internal state of the port #7FFD not change.

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Thank. Actually I implement PENTAGON 1024 and ZX PROFI 1024 memory paging to my PROFI INTERFACE :v2_wink2:

Result of execution on Pentagon1024SL2.2
18
82
18
16
17
17
113

Цитата:

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Сообщение от DDp

Result of execution on Pentagon1024SL2.2
18
82
18
16
17
17
113

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Emulator UNREAL SPECCY return this values:

82
82
82
16
17
17
17

Your BASIC program:
http://velesoft.speccy.cz/other/pentagon-paging.gif

VELESOFT, IMHO in the Pentagon-1024SL v.2.2 management D2 #EFF7 was not done correctly. In Unreal also not true. It should be:
82
82
82
16
17
17
81

Цитата:

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Сообщение от БК-0010

VELESOFT, IMHO in the Pentagon-1024SL v.2.2 management D2 #EFF7 was not done correctly. In Unreal also not true. It should be:
82
82
82
16
17
17
81

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It is tested on real machine ?

Цитата:

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Сообщение от VELESOFT

It is tested on real machine ?

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Is tested on a real head. Pentagon-1024SL and Unreal contain errors. I also made a mistake. Should be:
82
82
82
80
81
81
81

It SHOULD NOT be as shown by БК-0010 because D2 #eff7 is 128K compatibility bit.

Цитата:

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Сообщение от alone

It SHOULD NOT be as shown by БК-0010 because D2 #eff7 is 128K compatibility bit.

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:) Dima, there are no contradictions. Page installed in the window CPU3 not belong to the lower segment 128k. The implementation mode limits RAM to 128k does not matter what segment of 128k this page belongs :) . Restriction addressable RAM is not violated because the record in the register of addresses A17', A18' and A19' is locked. In this state of the register of upper addresses remain unchanged.