Сообщение от
http://www.thule.no/haynie/research/a3000p/docs/a3000p.pdf
5.3.2 Clock Signals
These are various clock signals useful for synchronous timing of video peripherals.
/C1 Clock
This is a 3.58 MHz clock (3.55 MHz on PAL systems) that’s synched to the falling edge
of the 7M system clock. Also known as /CCK in some places.
/C3 Clock
This is a 3.58 MHz clock (3.55 MHz on PAL systems) that’s synched to the rising edge
of the 7M system clock. Also known as /CCKQ in some places.
/C4 Clock
This is a 3.58 MHz clock (3.55 MHz on PAL systems) that’s synched to the rising edge
of the 7M CDAC clock.
CDAC Clock
This is a 7.16 MHz clock (7.09 MHz on PAL systems) that trails the 7M system clock by
90°.
C28O Clock
This is a 28.64MHz clock (28.36MHz on PAL systems) that’s synchonized to the digital
RBG bus.
Timer Time Base (TBASE)
This is the real time clock time-base input, either 50Hz or 60Hz depending on the country
involved and the setting of the Time Base Jumper. The jumper can select either line frequency
or vertical synchronization as the clock’s time base.
External Clock (XCLK, /XCLKEN)
The video slot provides for an external system clock, generally used to cause the entire
A2000 system to become synchronized to something external. This should be something very close to the 28.64 MHz clock normally used to drive the system; the value used for XCLK can be
a somewhat higher frequency, though anything too high will cause memory and other system
timings to break down. XCLK will only be engaged as the system clock when /XCLKEN is
asserted. There is no fixed phase relationship between XCLK and the internal clocks and video
output; C28O can always be used for pixel clocking.