ROM files structure

[Black_Cat]

My idea is join 4x 64kB rom (first 256kB) + one PROF-ROM (second 256kB).

ProfROM in the address space is seen as a 64K ROM.

---------- Post added at 01:11 ---------- Previous post was at 01:01 ----------

This interface can emulate memory paging of russian ZX clones (ZX PROFI, PENTAGON, SCORPION, etc...). TRDOS rom mapping will supported (work only with ramdisc in 1MB memory). All paging ports will readable, all features will changeable. For example - part of extended ram memory can emulate rom (will set to low 16kB as zx rom replacement with write protect). This enable modify zx roms, trdos , nmi menu, etc.....

Publish please port specification.

---------- Post added at 01:44 ---------- Previous post was at 01:11 ----------

I propose to use the following specification of ports:

#BDFD/48605  1011110111111101 10xxxx0xxx1xxx01 rd #1FFD
#BFDD/49117  1011111111011101 10xxxx1xxx0xxx01 rd #FE
#BFFD/49149  1011111111111101 10xxxx1xxx1xxx01 rd #7FFD

#EFF7 - rd/wr
wr D2#EFF7 - blkD5#7FFD             
wr D0#1FFD|D3#EFF7 r/wCPU0 MANAGETMENT
    0     | 0      rdROM 
    0     | 1      rdROM & wrRAM
    1     | 0      rwRAM
    1     | 1      rdRAM

for Pentagon, Scorpion, KAY, ZXM-Pxoenix:

A14"ROM Change Adress - D4 #7FFD 
A15"ROM Change Adress - D3 #1FFD 
A16"ROM Change Adress - D2 #1FFD 
A17"ROM Change Adress - D6 #1FFD 
A18"ROM Change Adress - D5 #1FFD

for DOS mode ZX Spectrum +2a,b/+3:

A14"ROM Change Adress - D4 #7FFD 
A15"ROM Change Adress - D2 #1FFD 
A16"ROM Change Adress = 1 
A17"ROM Change Adress - D6 #1FFD 
A18"ROM Change Adress - D5 #1FFD

[VELESOFT]

Publish please port specification.

PROFI IF is actually in development and contain reprogrammable CPLD. All features and ports can be modified during development.

My first upgrade is PENTAGON INTERFACE:
http://velesoft.speccy.cz/pentagon512_interface.htm


PROFI INTERFACE will compatible, but more powerfull
New NMI button will jump to extra NMI menu without rewriting memory on stack pointer (it's planned feature). I/O adress space can be mirrored to extra memory and user can read from memory last writed values to ports
Possibility block extra memory for users (128kB only) and enable extra memory (1MB) only for trdos rom (ramdisc will protected).
Advanced memory paging in low 16kB (as rom replacement) = DivIDE emulation
INFO ABOUT DIVIDE INTERFACE:
http://velesoft.speccy.cz/zx/divide/index.htm

I propose to use the following specification of ports:

#BDDD/48637  1011110111111101 10xxxx0xxx0xxx01 rd #DFFD
#BDFD/48605  1011110111111101 10xxxx0xxx1xxx01 rd #1FFD
#BFDD/49117  1011111111011101 10xxxx1xxx0xxx01 rd #FE
#BFFD/49149  1011111111111101 10xxxx1xxx1xxx01 rd #7FFD

Yes, it can be implemented to PROFI INTERFACE

---------- Post added at 21:07 ---------- Previous post was at 20:59 ----------

wr D2#EFF7 blkD5#7FFD(X)
wr D0#1FFD|D3#EFF7 r/wCPU0 MANAGETMENT
0 | 0 rdROM
0 | 1 rdROM & wrRAM
1 | 0 rwRAM
1 | 1 rdRAM

A14"ROM Change Adress - D4 #7FFD
A15"ROM Change Adress - D3 #1FFD
A16"ROM Change Adress - D2 #1FFD
A17"ROM Change Adress - D6 #1FFD
A18"ROM Change Adress - D5 #1FFD
[/code]

I will support more different rom paging ports:
DIVIDE rom memory on port 227
MB02 rom memory on port 23
ZX rom memory on port 7FFD/1FFD (+2A/+3/Scorpion)

1MB Ram paging ports:
7FFD (Pentagon 1024)
7FFD+1FFD (Scorpion)
7FFD+DFFD (ZX PROFI)

MB02 PAGING PORT 23:
port layout:
D0-D4 - number of 16kB rom/sram page (0-31)
D5 - 1=write enable or 0=write protect low 16kB memory
D6 - 1=connect sram memory (only if D7=0)
D7 - 1=connect rom memory (only if D6=0)

If D6=0 and D7=0 then will MB02 memory disabled and ZX rom is connect in
low 16kB

If D6=1 and D7=1 then will reset Z80CPU + disabled ZX rom + connect
external MB02 rom page 0 with write protect (set memory port to value #80)

[Black_Cat]

PROFI INTERFACE

It's his name?

New NMI button will jump to extra NMI menu without rewriting memory on stack pointer (it's planned feature).

More please..

I/O adress space can be mirrored to extra memory and user can read from memory last writed values to ports

What page number ROM? What is the structure of the record?

[VELESOFT]

It's his name?

Yes

More please..

After NMI will disconnect ZX memory and CPU adress will writed to new extra memory.

What page number ROM? What is the structure of the record?

Profi interface will use one 64kB memory block as I/O mirror area.
For example:
After OUT #7FFD,#10 will writed to adress #7FFD in extra memory value #10. (it's 16bit mode)
In 8bit mode: after OUT #7FFD,#10 will writed to adress #FD (accept only low 8bit adress) value #10. After connect this extra memory is possible read last writed values from identical adress.

[Black_Cat]

After NMI will disconnect ZX memory and CPU adress will writed to new extra memory.

To use PROFI INTERFACE need to change the scheme ZX Spectrum?

---------- Post added at 19:50 ---------- Previous post was at 19:48 ----------

In 8bit mode: after OUT #7FFD,#10 will writed to adress #FD (accept only low 8bit adress) value #10. After connect this extra memory is possible read last writed values from identical adress.

And what about the #FE?

[VELESOFT]

To use PROFI INTERFACE need to change the scheme ZX Spectrum?

Only CPU, ROM and HAL chips must be in socket. PROFI INTERFACE is connect to this three sockets. From ZX must be removed only one diode (for disable access to port 7FFD) and disable signal /CAS to 64kB of fast dram in ZX+2(or remove 8 DRAM chips from sockets)

And what about the #FE?

About #FE or #FD ???
This is only example of possibility. On real PROFI INTERFACE willl extra decoder for all paging ports.

[Advertiser]

[Black_Cat]

On real PROFI INTERFACE willl extra decoder for all paging ports.

Why use 64K of RAM if the decoder? To save the state of all system ports and all the CPU registers rather 64 bytes of RAM.

[VELESOFT]

Why use 64K of RAM if the decoder? To save the state of all system ports and all the CPU registers rather 64 bytes of RAM.

This feature can be used or disabled. With mirror adress space is possible show all 65536 ports (state of all ZX ports - for all ZX interfaces with any ports).

[Black_Cat]

With mirror adress space is possible show all 65536 ports (state of all ZX ports - for all ZX interfaces with any ports).

What is the address for reading the port #FE?

---------- Post added at 23:47 ---------- Previous post was at 23:42 ----------

+2A and +3 use identical 64kB rom. A16-A18 not exist.

This is the address of the address space ROM drive, rather than a specific ROM.

[VELESOFT]

What is the address for reading the port #FE?

---------- Post added at 23:47 ---------- Previous post was at 23:42 ----------

This is the address of the address space ROM drive, rather than a specific ROM.

Actually not defined this adress.