Pentagon 48 или GRM1 начало INTа

[solegstar]

This is how I modified the board:

after these changes, did the synchronization return to normal?

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[Shockwav3]

Yes, everything back to normal after I removed the additional AND-Gates and put everything back into place.


Just for the sake of it, these are my attempts to "translate" the P128 schematics to P48 to make things a bit easier to compare.
So far I've found nothing overly different

[solegstar]

additional AND-Gates

Did you mean an additional 74ls32 (OR-Gates), or did you have something else additionally installed?

[Shockwav3]

Sorry, I meant OR-Gates of course.

[Shockwav3]

Currently experimenting with the circuit proposed by LEN2PEN2.TXT (Output of DD6.3 [Pin8] through 1.2K resistor -> 6.8n capacitor tied to ground + inverter -> !INT on Z80) I'm getting something extremely close to a correct timing for the Rage endpart (can't see any offset while it's moving and the "paper wobble" at the beginning actually looked correct, with the screen standing it's 1px) - only problem, this only happens on every second or third reset.
I also did replace D40 with a 74ALS174 (because I managed to break off a pin off my 74LS174).


This is how the circuit is currently modified:


EDIT: Looks like I'm not quite done yet ... on a second testrun the border was 1 pixel late (instead of early), TestINT no longer reports a value and BorderCreate simply crashes.

[Shockwav3]

Looks like I finally got it right!
I've now managed to move the paper a bit to the right and it lines up except for 1 pixel. This was done by recreating the clock0 for DD9 as done in the P128 (your approach in post #29 was almost right solegstar).
BorderCreate, Rage Endpart, TestINT, Eyeache/Alienate are all working fine

In case anyone wants to fix their Pentagon48 for 128 timing, here are the modifications I did:
vertical adjustment of INT:


horizontal adjustment of INT:


!WRFE

EDIT: 4.7nF for 74LS/555 series

[solegstar]

I've now managed to move the paper a bit to the right and it lines up except for 1 pixel. This was done by recreating the clock0 for DD9 as done in the P128 (your approach in post #29 was almost right solegstar)

my congratulations!!! and it is strange that my circuit does not work. The logic of both schemes is the same. a logical zero will appear at the output only when all three inputs are zero. logical operation OR 74als32 fits perfectly on a single chip, instead of two NOR and NAND.

[zebest]

I've now managed to move the paper a bit to the right and it lines up except for 1 pixel.

Fine!
на один пиксель сложно подвинуть)
Не знаю как на реальном железе, но в FPGA я подвинул на 1 pixel инвертированием тактового сигнала для этого узла)) Ну как бы на пол-такта получилась задержка. В плис такой фокус сработал, в Speccy2010 картинка на бордюре идеальная. Была(. Ну это так, для перфекционистов.

[Shockwav3]

Yeah, one pixel is fine for me for the moment I think inverting (part of) a signal or adding a delay/pullup/pulldown might fix it, but for the moment I'm done experimenting ... I'll get back to it in a few days once I finalize my INT + Mem + AY (+ Covox? [+ Kempston?]) interface.

@solegstar: I'll get back to that as it's currently just a prototyping circuit. On my intended addon card (currently it's a bunch of loose wires and breadboard) I still have a few gates for spare (1x LS02, 2x LS32, 1x Flip-Flop from LS74)


EDIT: Adding 2.2nF against ground on the output of the inverter for !WRFE fixed things ... seems kinda finicky (changing between 74/74LS/74ALS [155/555/1533] chip families still breaks things - currently I'm going with a 155LA3) but works well enough for me.

[romke]

Shockwav3, спасибо за схемы!

HINT себе сделал вот так:


WRFE пока не дорабатывал. К сожалению половина кнопок не работает на клавиатуре, немогу проверить на тестах((.