ADDRESS_REG_B=CLOCK1
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS
INDATA_REG_B=CLOCK1
INIT_FILE=rom0.hex
INIT_FILE_LAYOUT=PORT_A
INTENDED_DEVICE_FAMILY="Cyclone III"
LPM_TYPE=altsyncram
NUMWORDS_A=16384
NUMWORDS_B=8192
OPERATION_MODE=BIDIR_DUAL_PORT
OUTDATA_ACLR_A=NONE
OUTDATA_ACLR_B=NONE
OUTDATA_REG_A=UNREGISTERED
OUTDATA_REG_B=UNREGISTERED
POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
WIDTHAD_A=14
WIDTHAD_B=13
WIDTH_A=8
WIDTH_B=16
WIDTH_BYTEENA_A=1
WIDTH_BYTEENA_B=1
WRCONTROL_WRADDRESS_REG_B=CLOCK1
DEVICE_FAMILY="Cyclone III"
address_a
address_b
clock0
clock1
data_a
data_b
wren_a
wren_b
q_a
q_b
