Различия в поведении команд на разных процессорах
Приложение из документации по PDP-11/94 по различиям в поведении инструкций на разных процессорах.
Вложений: 1
Power-Up/Power-Down timing
Пока готовлю БП с полным управлением с передней панели, чтоб не потерялось, закину сюда (выдержка из описания KDJ11-B)...
Power-Up - The timing diagram for the power-up/power-down sequence is shown in Figure 6-13. The following events occur during a power-up sequence.
- Logic associated with the power supply negates BDCOK H during power-up and asserts BDCOK H 3 ms (minimum) after dc power is restored to voltages within specification.
- The processor asserts BINIT L after receiving nominal power and negates BINIT L 0 ns (minimum) after the assertion of BDCOK H.
- Logic associated with the power supply negates BPOK H during power-up and asserts BPOK H 70 ms (minimum) after the assertion of BDCOK H. If power does not remain stable for 70 ms, BDCOK H is negated. Therefore, devices must suspend critical actions until BPOK H is asserted.
- BPOK H must remain asserted for a minumum of 3 ms. BDCOK H must remain asserted 4 ms (minimum) after the negation of BPOK H.
Power-Down - The following events occur during a power-down sequence.
- If the ac voltage to a power supply drops below 75% of the nominal voltage for one full line cycle (15 to 24 ms), BPOK H is negated by the power supply. Once BPOK H is negated, the entire power-down sequence must be completed.
A device that requested bus mastership before the power failure that has not become bus master must maintain the request until BINIT L is asserted or the request is acknowledged (in which case regular bus protocol is followed). - Processor software must execute a RESET instruction 3 ms (minimum) after the negation of BPOK H. This asserts BINIT L for 8 to 20 us. Processor software executes a HALT instruction immediately following the RESET instruction.
- BDCOK H must be negated a minimum of 4 ms after the negation of BPOK H. This 4 ms allows mass storage and similar devices to protect themselves against erasures and erroneous writes during a power failure.
