omercury, Касательно SDRAM, вот это на моей борде заработает? https://github.com/stffrdhrn/sdram-controller
Память hy57v561620
Вид для печати
omercury, Касательно SDRAM, вот это на моей борде заработает? https://github.com/stffrdhrn/sdram-controller
Память hy57v561620
В xilinx вывод pin INOUT можно сделать как clock ? Что то он в timing cinstraint видится только как оutput
В xilinx надо смотреть на свойства конкретного вывода. Обычно (практически всегда) вывод плисы для входного clok'a "выделен". Другими словами на "inout обычный" входной тактовый сигнал крайне не рекомендуется подвать. Тактовый подают на вывод который есть MCLK или SCLK (примерные названия).
ПС: ise или vivado ?
AlexG, ise , она такие маневры видимо не любит с inout на тактовой входе , задумка была такая - есть общий генератор ,например 50мгц , плис делит его например на 2 , и эти 25 МГц надо вывести из плис на тактовую проца но и в плисине этот сигнал должен остаться как тактовый , вот думал таким образом пролезет использование тактового пина на inout
JV-Soft, не знаю как в Xilinx, но в Altera такое запросто. "Половинной" частотой управляется контроллер SDRAM, и она же выведена на inout для микросхемы.
Bolt, и этот вывод глобальный клок ?
Дык вы ж не сказали что хотите "выход тактовой".Цитата:
Сообщение от JV-Soft
тактовую подают на спец вход MCLK, в самой плисе клок идёт на "pll", там оная частота умножается/делится и "пучёк" разных тактовых раздаётся "нуждающимся", можно вывести на любой выход плис (который может быть выходом). и не забываем что оная тактовая может иметь "случайную" фазу.
Курите доку на свой чипс в разделе - Clock and PLL Pins.Цитата:
Сообщение от JV-Soft
Нет, что первое попалось :)Цитата:
Сообщение от JV-Soft
К AlexG добавлю.
Тактовые пины и шины имеют меньшую задержку. Правильнее делать через выделенные, но можно и на обычных, просто надо учитывать что это может не пройти по задержкам и частотам. Анализатор у меня пишет 110 МГц, SDRAM на 75 работает. Для "видеокарты" вообще сложным счётчиком делаю тактовую 25.175 из 100. А с процессора идёт своя синхронизация CPU_PHI, которую завёл тоже на первый попавшийся.
Привет всем. Пробую сделать rom-картридж (не спрашивайте зачем :) ), аналог ZXC2 http://www.fruitcake.plus.com/Sincla...e2_RC_ZXC2.htm
Идея такая, выдаем на спек 0 на ресет (что все шины Z80 перешли в высокоимпедансное состояние), и с SD карты записываем в микросхему SRAM бинарник от картриджа, посредством микроконтроллера. Адрес записи для SRAM (128кБ) формируем 17 разрядным счетчиком на ПЛИС, посредством сигналов clock и clear от микроконтроллера. После записи, переводим шину данных контроллера в высокоимпедансное состояние и снимаем ресет со спека. При условии сигнала ресет в 1 логика должна работать как в оригинальном картридже. Данные в SRAM пишутся стабильно, при отладке сливал дамп со SRAM по юсарту и сравнивал с исходным бинарником, все ок. Но вот при состоянии ресет в 1, в "железе" не работает. Где то я тут напортачил (это первый мой код на VDHL :D ), прога компилируется без ошибок, но с кучей варнингов. Похоже я не очень понимаю суть оператора Process. Помогите разобраться пожалуйста.
ВаринингиКод:library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ram_vdhl is
port
(
clock : in std_logic;
clear : in std_logic;
a_ram_l : inout std_logic_vector(13 downto 0);
a_ram_h : out std_logic_vector(2 downto 0);
reset : in std_logic;
mreq : in std_logic;
ce_mcu : in std_logic;
oe_mcu : in std_logic;
romcs : out std_logic;
oe_ram : out std_logic;
ce_ram : out std_logic;
a14_zx : in std_logic;
a15_zx : in std_logic
);
end ram_vdhl;
architecture ram_vdhl_arc of ram_vdhl is
signal count: std_logic_vector(16 downto 0):= (others => '0');
signal zxc: std_logic_vector(5 downto 0):= (others => '0');
signal oe: std_logic;
signal adr: std_logic;
signal clk: std_logic;
begin
A:process (clock, clear)
begin
if clear = '1' then
count <= (others => '0');
elsif (rising_edge(clock)) then
count <= count +1;
end if;
end process;
B:process (reset)
begin
if reset = '1' then
a_ram_l(13 downto 0) <= "ZZZZZZZZZZZZZZ";
oe <= (a14_zx or a15_zx or mreq);
adr <= not (a_ram_l(6) and a_ram_l(7) and a_ram_l(8) and a_ram_l(9) and a_ram_l(10) and a_ram_l(11) and a_ram_l(12) and a_ram_l(13));
clk <= not (oe or adr or zxc(0));
oe_ram <= oe;
a_ram_h(0) <= zxc(3);
a_ram_h(1) <= zxc(1);
a_ram_h(2) <= zxc(5);
ce_ram <= zxc (4);
romcs <= zxc (4);
else
a_ram_l <= count(13 downto 0);
a_ram_h <= count(16 downto 14);
oe_ram <= oe_mcu;
ce_ram <= ce_mcu;
end if;
end process;
C:process (clk)
begin
if (rising_edge(clk)) then
zxc(0) <= a_ram_l(5);
zxc(1) <= a_ram_l(1);
zxc(2) <= a_ram_l(3);
zxc(3) <= a_ram_l(0);
zxc(4) <= a_ram_l(4);
zxc(5) <= a_ram_l(2);
end if;
end process;
end ram_vdhl_arc;
Ну или может книжку хорошую порекомендуете по VDHL для ПЛИС, пока только кривые "ПЛИС с нуля" в инете находятся.Код:Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Feb 14 23:09:04 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM_VDHL -c RAM_VDHL
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file ram_vdhl.vhd
Info (12022): Found design unit 1: ram_vdhl-ram_vdhl_arc
Info (12023): Found entity 1: ram_vdhl
Info (12127): Elaborating entity "RAM_VDHL" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(47): signal "a14_zx" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(47): signal "a15_zx" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(47): signal "mreq" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(48): signal "a_ram_l" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(49): signal "oe" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(49): signal "adr" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(49): signal "zxc" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(50): signal "oe" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(51): signal "zxc" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(52): signal "zxc" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(53): signal "zxc" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(54): signal "zxc" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(55): signal "zxc" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(57): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(58): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(59): signal "oe_mcu" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at RAM_VDHL.vhd(60): signal "ce_mcu" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at RAM_VDHL.vhd(43): inferring latch(es) for signal or variable "oe", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at RAM_VDHL.vhd(43): inferring latch(es) for signal or variable "adr", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at RAM_VDHL.vhd(43): inferring latch(es) for signal or variable "clk", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at RAM_VDHL.vhd(43): inferring latch(es) for signal or variable "romcs", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "romcs" at RAM_VDHL.vhd(43)
Info (10041): Inferred latch for "clk" at RAM_VDHL.vhd(43)
Info (10041): Inferred latch for "adr" at RAM_VDHL.vhd(43)
Info (10041): Inferred latch for "oe" at RAM_VDHL.vhd(43)
Info (19000): Inferred 1 megafunctions from design logic
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=17) from the following logic: "count_rtl_0"
Info (12130): Elaborated megafunction instantiation "lpm_counter:count_rtl_0"
Info (12133): Instantiated megafunction "lpm_counter:count_rtl_0" with the following parameter:
Info (12134): Parameter "LPM_WIDTH" = "17"
Info (12134): Parameter "LPM_DIRECTION" = "UP"
Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER"
Info (280013): Promoted pin-driven signal(s) to global signal
Info (280014): Promoted clock signal driven by pin "clock" to global clock signal
Info (280016): Promoted output enable signal driven by pin "reset" to global output enable signal
Info (21057): Implemented 61 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 8 input pins
Info (21059): Implemented 6 output pins
Info (21060): Implemented 14 bidirectional pins
Info (21063): Implemented 31 macrocells
Info (21073): Implemented 2 shareable expanders
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 22 warnings
Info: Peak virtual memory: 351 megabytes
Info: Processing ended: Fri Feb 14 23:09:08 2020
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:02
Info: *******************************************************************
Info: Running Quartus II 32-bit Fitter
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Feb 14 23:09:09 2020
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM_VDHL -c RAM_VDHL
Info: qfit2_default_script.tcl version: #1
Info: Project = RAM_VDHL
Info: Revision = RAM_VDHL
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EPM7032SLC44-10 for design "RAM_VDHL"
Info: Quartus II 32-bit Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 312 megabytes
Info: Processing ended: Fri Feb 14 23:09:11 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Feb 14 23:09:14 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM_VDHL -c RAM_VDHL
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 307 megabytes
Info: Processing ended: Fri Feb 14 23:09:15 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Feb 14 23:09:16 2020
Info: Command: quartus_sta RAM_VDHL -c RAM_VDHL
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (306004): Started post-fitting delay annotation
Info (306005): Delay annotation completed successfully
Warning (335095): TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'RAM_VDHL.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name clock clock
Info (332105): create_clock -period 1.000 -name a14_zx a14_zx
Warning (332125): Found combinational loop of 2 nodes
Warning (332126): Node "romcs$latch~6|[2]"
Warning (332126): Node "romcs$latch~6|dataout"
Warning (332125): Found combinational loop of 2 nodes
Warning (332126): Node "clk~10|dataout"
Warning (332126): Node "clk~10|[1]"
Warning (332125): Found combinational loop of 2 nodes
Warning (332126): Node "adr~10|dataout"
Warning (332126): Node "adr~10|[1]"
Warning (332125): Found combinational loop of 2 nodes
Warning (332126): Node "oe~10|[1]"
Warning (332126): Node "oe~10|dataout"
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -9.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -9.000 -153.000 clock
Info (332146): Worst-case hold slack is 5.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 5.000 0.000 clock
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -3.500
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): -3.500 -119.000 clock
Info (332119): -3.500 -35.000 a14_zx
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 16 warnings
Info: Peak virtual memory: 280 megabytes
Info: Processing ended: Fri Feb 14 23:09:17 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Feb 14 23:09:18 2020
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off RAM_VDHL -c RAM_VDHL
Info (204019): Generated file RAM_VDHL.vo in folder "D:/ZX SPECTRUM/rom_cartridge/RAM_ZX2_VDHL_copy/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 290 megabytes
Info: Processing ended: Fri Feb 14 23:09:19 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00
Info (293000): Quartus II Full Compilation was successful. 0 errors, 39 warnings