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[ZEK]

Ewgeny7 погоняй на скорпэве, Дмитрий завтра появиться попробуем попросить его собрать бин для пентевы

`timescale 1ns/10ps

module pll28(
    input   wire        clk,   // 28mhz
    input   wire        rddat_n,
    output  reg         rclk,
    output  reg         rawr_n
    );

// filter
reg [3:0] sr;           
reg       rawr_sync;

always @ (posedge clk)
begin
    sr <= { sr[2:0], rddat_n }; 
    if (sr == 4'hF || sr == 4'h0)
        rawr_sync <= sr[3];    
end

// rawr
reg [4:0] rawr_sr;

always @ (posedge clk)
begin
    rawr_sr <= { rawr_sr[3:0], rawr_sync };
    rawr_n  <= !(rawr_sr[4] && !rawr_sr[0] ); // rawr 140ns
end

// rclk  
reg [5:0] counter = 0;                     
wire[5:0] delta = 27 - counter; 
wire[5:0] shift = { delta[5], delta[5], delta[4:1] }; // sign div
wire[5:0] inc   = rawr_sr[1:0] == 2'b10 ? shift : 1;

always @ (posedge clk)
begin               
    if (counter < 55)
        counter <= counter + inc;   
    else           
    begin             
        counter <= 0;
        rclk = ~rclk;  
    end
    
end

initial 
    rclk = 0;

endmodule