The contended memory timings differ on the +2A/+3 from the earlier machines; firstly, the timing differences mean that the top-left pixel of the screen is displayed 14364 T-states after the 50 Hz interrupt occurs, as opposed to 14336. The T-states (relative to the interrupt) at which delays occur are given in the following table:
Cycle # Delay
------- -----
14365 1
14366 No delay
14367 7
14368 6
14369 5
14370 4
14371 3
14372 2
14373 1
14374 No delay
14375 7
14376 6
and so on, until cycle 14494, when the display of the first scanline on the screen has been completed, and no more delays are inserted until 14593 (=14365+228) when the cycle repeats. The other difference occurs for instructions which have multiple 'pc+1' or 'hl' entries in the breakdown for the other machines: on the +2A/+3, these entries are combined into just one. This means that, for example, JR becomes pc:4,pc+1:8.
Unlike the base 128K machine, RAM banks 4, 5, 6 and 7 are contended. However, Port 0xfe is not; whether ports 0x7ffd and 0x1ffd are contended is currently unknown.
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