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Сигнал IORQULA ни в DivMMC, ни в DivIDE не формируется.
The IORQ signal generated by the Z80 is connected to the IOREQ input of the ULA via a series resistor allowing the IOREQ pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low.

This combined IORQ+A0 signal is connected to Lower Pin 13 and is referred to as IORQULA or sometimes IORQGE.