Шиздец... Я спрашиваю о том чего уже нет , пересэтэ...
Даже с основного сайта все сырки поубирал... Злобный партизанен
Собсно вот (в аттаче) , там только сырок , ибо весь проэкт состоящий из мусора в запакованном виде занимает аж полтара мега...
Если кому нужен фаил с распиновкой чипа , то скажите какое у него расширение , а то файлов где торчит распиновка просто дофигища .
Чуть не забыл - в файле залочена всякая там билиберда вроде RS232/кемпстона и оставлен SPI . Но это не значит что компилироваться будет только под SPI , чтоб было только под SPI нужно либо закоментировать , либо прибить всё лишнее , иначе только ячейки зря отжираться будут .
Как разлочить RS232 и прочее ниписано внутри файла .
Старая описака -
The project fits into a Xilinx's XC9572XL 3.3V cpld, 5V tolerant. This component is well suited for interfacing the 5V ZX-Spectrum logic to 3.3V sd/mmc card logic. The picture above shows the cpld in VQ44 package, which is used in the project.
After programming through the JTAG header, the CPLD will work as an SPI device on I/O port $3F.
The 115K2baud RS-232, NMI handling and Kempston Joystick ports, who are present in the zx-badaloc version, are disabled by default in order to avoid conflicts with existing hardware. These features can be easily enabled by programming the alternate JEDEC file.
Port List for the STANDARD version:
$1F: WR = 2 bit chip select register (D0 = MMC0; D1 = MMC1), active LOW
$3F: WR = SPI TX register; RD = SPI RX register (8 bit)
Port List for the FULL version:
$0F: WR = RS-232 TX register; RD = RS-232 receive register (8 bit)
$1F: RD = KEMPSTON PORT (5 bit, '1' = input active); WR = 2 bit chip select register (D0 = MMC0; D1 = MMC1), active LOW
$2F: WR = D0: 0 = NMI disabled; 1 = enabled. RD = read RS232 status (4 bit)
$3F: WR = SPI TX register; RD = SPI RX register (8 bit)
STATUS REGISTER ($2F):
D0: 0 = receiver empty; 1 = receiver has data
D1: 0 = no error; 1 = overrun
D2: 0 = no error; 1 = framing error
D3: 0 = transmitter idle (ready); 1 = transmitter full
Further details can be found in the VHDL source code. Please note that the SPI-only version still has WRITE ENABLED on all ports. This means that a byte written to port $0F will be sent through the rs-232 TX pin in all versions. READING is disabled on all ports but $3F. Chip selects control is then assured by writing to port $1F in all versions (D0 = MMC0, D1 = MMC1). Internal CPLD logic avoids simultaneous chip select activation: in case "00" is written to this register: MMC0 takes over (MMC1 chip select will be forced HIGH). Both chip selects are in HIGH (inactive) state at power-on.
When the processor reads one of the above I/O ports for the full version, or the SPI port for the standard version, the corresponding data is placed on databus.
When the processor writes to one of the above I/O ports, then the CPLD starts an internal counter that latches databus status into proper internal register on the falling edge of T3 cycle, which is right in the middle of the write operation. Since IORQ and WR are issued on the rising edge of main clock (on T2), the internal logic (counter and latches) works on falling edge in order to guarantee reliability in the count process.
This diagram shows a write cycle to port $3F, which is the SPI OUT register. For debug purposes, a "capture" signal has been configured on the CS1 pin (unused), that goes high when data is latched (which happens on the falling edge of T3 cycle, as stated above). The diagram also shows how the byte is transferred to the SD.MMC card in the following 16T-states (SPI CLOCK is toggled on each Z80 T-state). The byte written to port $3F was "$55".
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