ПЛИС и всё что с ними связано

[dosikus]

omercury, Пришлось отложить все до выходных -на работе был завал .

Прикрутил к своему топу на VHDL, выставил 800х600.
В настройках vpll - вижу - c0 540MHz , с1 -108MHz , - где я напортачил?

Картинко

[свернуть]

Топ такой:

Код в VHD

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity test_top is
    port(
        -- master clock 50.0 MHz
        CLK_50MHZ   : in std_logic;

        -- HDMI
        TMDS        : out std_logic_vector(7 downto 0);

        -- USB Host (VNC2-32)
        USB_NRESET  : in std_logic);


  
end test_top;

architecture rtl of test_top is
    
    signal reset : std_logic;
    signal areset : std_logic;
    signal locked0 : std_logic;

    signal clk_vga : std_logic;
    signal clk_tmds : std_logic;
    signal clk_spi : std_logic;

    signal vga_hsync: std_logic;
    signal vga_vsync: std_logic;
    signal vga_blank : std_logic;
    signal vga_r : std_logic_vector(7 downto 0);
    signal vga_g : std_logic_vector(7 downto 0);
    signal vga_b : std_logic_vector(7 downto 0);
	 
	 signal vga_out : std_logic_vector(7 downto 0);
	 
	 signal hcnt		: std_logic_vector(11 downto 0) := "000000000000"; 	-- horizontal pixel counter
    signal vcnt		: std_logic_vector(11 downto 0) := "000000000000"; 	-- vertical line counter
	 signal shift		: std_logic_vector(7 downto 0);
	 
	 signal  px_y     : std_logic_vector(9 downto 0);
	 signal  px_x     : std_logic_vector(9 downto 0);
	 signal  vaddr    : std_logic_vector(19 downto 0);
	 


component vga_sync 
port (

clk_in : in std_logic;                   -- Input 25.175 MHz clock, this is a pixel clock for this VGA mode


picselclock : out std_logic;            -- Output horizontal sync signal
hdmi_clock : out std_logic;           -- Output vertical sync signal

vga_hsync : out std_logic;            -- Output horizontal sync signal
vga_vsync : out std_logic;           -- Output vertical sync signal

disp_enable: out std_logic;          -- Set when a writable portion of display is enabled:


v_addr : out std_logic_vector(7 downto 0)
      );
end component;


begin


            
                                 

    U_HDMI: entity work.hdmi
        generic map (
            FREQ        => 25200000,
            FS          => 48000,
            CTS         => 25200,
            N           => 6144)
        port map (
            I_CLK_VGA   => clk_vga,
            I_CLK_TMDS  => clk_tmds,       -- 472.6 MHz max
            I_HSYNC     => not vga_hsync,
            I_VSYNC     => not vga_vsync,
            I_BLANK     => not vga_blank,
            I_RED       => vga_out(7 downto 5)& vga_out(7 downto 5)& vga_out(7 downto 6),
            I_GREEN     => vga_out(4 downto 2) & vga_out(4 downto 2)& vga_out(4 downto 3),
            I_BLUE      => vga_out(1 downto 0) & vga_out(1 downto 0)& vga_out(1 downto 0)& vga_out(1 downto 0),
            I_AUDIO_PCM_L   => "0000000000000000",
            I_AUDIO_PCM_R   => "0000000000000000",
            O_TMDS      => TMDS);

				
				
				VGA_SYN: vga_sync
				 port map(
					clk_in =>CLK_50MHZ,
					picselclock => clk_vga,
					hdmi_clock => clk_tmds,
				    vga_hsync => vga_hsync,
				    vga_vsync => vga_vsync,
				    disp_enable	=>  vga_blank,
					v_addr =>vga_out
					 );
	 
	 

end rtl;

[свернуть]

- - - Добавлено - - -

UP , ставлю 640х480 - настройки PLL не меняются , те же 540 и 108...


И еще - где в Quartus выбирается кодировка? Все комменты на кириллице пох***ись...