ПЛИС и всё что с ними связано

[omercury]

I_RED => vga_out(7 downto 5)& vga_out(7 downto 5)& vga_out(7 downto 6),
I_GREEN => vga_out(4 downto 2) & vga_out(4 downto 2)& vga_out(4 downto 3),
I_BLUE => vga_out(1 downto 0) & vga_out(1 downto 0)& vga_out(1 downto 0)& vga_out(1 downto 0),

assign I_RED = {vga_out[7:5], vga_out[7:5], vga_out[7:6]};
assign I_GREEN = {vga_out[4:2], vga_out[4:2], vga_out[4:3]};
assign I_BLUE = {vga_out[1:0], vga_out[1:0], vga_out[1:0], vga_out[1:0]};

ругается что-то насчет неупакованного массива
...
reg vaddr[7:0];

Гы..!
wire

[Advertiser]

[dosikus]

omercury, туплю, помоги :

module vga_gen
(
input wire clk_50MHz,
output wire [7:0] TMDS

);


wire h_sync;
wire v_sync;
wire picselclock;
wire hdmi_clock;
wire blank;
wire vaddr[7:0];


vga_sync VGA_SYN
( .clk_in (clk_50MHz),
.picselclock(picselclock) ,
.hdmi_clock(hdmi_clock),
.vga_hsync (h_sync),
.vga_vsync (v_sync),
.disp_enable (blank),
.v_addr (vaddr)
);




hdmi #(
.FREQ(5200000),
.FS(48000),
.CTS(25200),
.N(6144))
HDMI1 (
.I_CLK_VGA (picselclock),
.I_CLK_TMDS (hdmi_clock),
.I_HSYNC (h_sync),
.I_VSYNC (v_sync),
.I_BLANK (~blank),
//.I_RED (8'b11111111),
.I_RED (),
.I_GREEN (),
.I_BLUE (),
.I_AUDIO_PCM_L (1'b0),
.I_AUDIO_PCM_R (1'b0),
.O_TMDS (TMDS)
);

assign I_RED = { vaddr[7:5], vaddr[7:5], vaddr[7:6]};
assign I_GREEN = { vaddr[4:2], vaddr[4:2], vaddr[4:3]};
assign I_BLUE = { vaddr[1:0], vaddr[1:0], vaddr[1:0], vaddr[1:0]};

endmodule

Warning (10236): Verilog HDL Implicit Net warning at vga_gen.v(56): created implicit net for "I_RED"
Warning (10236): Verilog HDL Implicit Net warning at vga_gen.v(57): created implicit net for "I_GREEN"
Warning (10236): Verilog HDL Implicit Net warning at vga_gen.v(58): created implicit net for "I_BLUE"
Error (10044): Verilog HDL error at vga_gen.v(30): expression cannot reference entire array "vaddr"
Error (10048): Verilog HDL error at vga_gen.v(30): values cannot be assigned directly to all or part of array "vaddr" - assignments must be made to individual elements only
Error (10133): Verilog HDL Expression error at vga_gen.v(56): illegal part select of unpacked array "vaddr"
Error (10133): Verilog HDL Expression error at vga_gen.v(57): illegal part select of unpacked array "vaddr"
Error (10133): Verilog HDL Expression error at vga_gen.v(58): illegal part select of unpacked array "vaddr"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 5 errors, 3 warnings
Error: Peak virtual memory: 4622 megabytes
Error: Processing ended: Sat Oct 05 15:42:10 2019
Error: Elapsed time: 00:00:09
Error: Total CPU time (on all processors): 00:00:09
Error (293001): Quartus II Full Compilation was unsuccessful. 7 errors, 3 warnings

- - - Добавлено - - -

Мда , досадная ошибка из-за невнимательности ...

Надо
wire [7:0] vaddr;

а не

wire vaddr[7:0];

[omercury]

туплю

Скрытый текст

module vga_gen
(
input wire clk_50MHz,
output wire [7:0] TMDS

);


wire h_sync;
wire v_sync;
wire picselclock;
wire hdmi_clock;
wire blank;
wire vaddr[7:0];


vga_sync VGA_SYN
( .clk_in (clk_50MHz),
.picselclock(picselclock) ,
.hdmi_clock(hdmi_clock),
.vga_hsync (h_sync),
.vga_vsync (v_sync),
.disp_enable (blank),
.v_addr (vaddr)
);




hdmi #(
.FREQ(5200000),
.FS(48000),
.CTS(25200),
.N(6144))
HDMI1 (
.I_CLK_VGA (picselclock),
.I_CLK_TMDS (hdmi_clock),
.I_HSYNC (h_sync),
.I_VSYNC (v_sync),
.I_BLANK (~blank),
//.I_RED (8'b11111111),
.I_RED (I_RED ),
.I_GREEN (I_GREEN),
.I_BLUE (I_BLUE),
.I_AUDIO_PCM_L (1'b0),
.I_AUDIO_PCM_R (1'b0),
.O_TMDS (TMDS)
);

wire [7:0] I_RED = { vaddr[7:5], vaddr[7:5], vaddr[7:6]};
wire [7:0] I_GREEN = { vaddr[4:2], vaddr[4:2], vaddr[4:3]};
wire [7:0] I_BLUE = { vaddr[1:0], vaddr[1:0], vaddr[1:0], vaddr[1:0]};

endmodule

[свернуть]

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Что ж так тормозит-то?