AlexBel off Igor_t on
Сообщение от
ewgeny7
AlexBel, ткни пжалуста носом в HDL-SPI какойнить попроще для фкуривания
только это Игорь ))))
нечто мудренное , если склероз неизменяет то это готовый модуль для работы с флешой типа 25хх
Код:
module spi
(
input clk,
input start,
input wr,
input wr_en,
output reg done,
input [7:0] spi_command,
input [15:0] spi_addres,
output reg [7:0] spi_data_out,
input [7:0] spi_data_in,
output reg spi_clk,
output reg spi_cs,
output reg spi_di,
input spi_do
);
initial done = 0;
initial spi_data_out = 8'h00;
initial spi_clk = 0;
initial spi_cs = 0;
initial spi_di = 0;
reg wr_en_reg;
reg wr_reg;
reg [7:0] spi_command_reg;
reg [15:0] spi_addres_reg;
reg [7:0] spi_data_in_reg;
reg [3:0] divider;
reg [1:0] mode;
reg [3:0] count_addr;
reg [2:0] count_data;
reg [1:0] delay_done;
always@ (posedge clk)
begin
if (start == 1'b1)
begin
if (divider < 4'd12 )
begin
divider <= divider + 1'b1;
if (divider == 4'd6)
begin
if (spi_clk == 1'b1)
begin
if (mode == 2'd0)
begin
count_data <= count_data + 1'b1;
if(count_data == 3'd7)
begin
if (wr_en_reg == 0)
begin
mode <= mode + 1'b1;
end
else
begin
mode <= 2'd3;
end
end
end
if (mode == 2'd1)
begin
count_addr <= count_addr + 1'b1;
if(count_addr == 4'd15)
begin
mode <= mode + 1'b1;
end
end
if (mode == 2'd2)
begin
count_data <= count_data + 1'b1;
if(count_data == 3'd7)
begin
mode <= mode + 1'b1;
end
if (wr_reg == 1'b0)
begin
if (spi_clk == 1'b1)
begin
spi_data_out[~count_data] <= spi_do;
end
end
end
end
else
begin
if (mode == 2'd3)
begin
spi_cs <= 1'b1;
spi_di <= 1'b0;
delay_done <= delay_done + 1'b1;
end
if(delay_done == 2'b11) done <= 1'b1;
end
end
end
else
begin
divider <= 4'd0;
if (spi_cs == 1'b0)
begin
spi_clk <= ~spi_clk;
end
end
if (mode == 2'd0)
begin
spi_di <= spi_command_reg[~count_data];
spi_cs <= 0;
end
if (mode == 2'd1)
begin
spi_di <= spi_addres_reg[~count_addr];
end
if (mode == 2'd2)
begin
if (wr_reg == 1'b1)
begin
spi_di <= spi_data_in_reg[~count_data];
end
else
begin
spi_di <= 1'b0;
end
end
end
else
begin
wr_en_reg <= wr_en;
divider <= 4'd0;
count_addr <= 4'd0;
count_data <= 3'd0;
mode <= 2'd0;
wr_reg <= wr;
delay_done <= 2'b00;
done <= 1'b0;
spi_command_reg <= spi_command;
spi_addres_reg <= spi_addres;
spi_data_in_reg <= spi_data_in;
spi_cs <= 1'b1;
spi_clk <= 1'b0;
spi_di <= 1'b0;
end
end
endmodule
блин а тег code тут работает ?????
Igor_t off
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