Compiling a Compact 256 Turbo partslist

Hi there,
I'm currently in the process of gathering parts for my Compact 256 Turbo PCB and have a few questions left

1.) What's the value of the coil? 10mH? 100mH?
2.) What's a suitable Zener Diode for the 12V supply? Would a 13V variant work?
3.) I'm having some issues reading the values for the ceramic capacitors on the board Here's a list of what I found and how I interpret them, would be cool if one of you could doublecheck them:
m15 = 150nF
n20 (near the 14MHz crystal) = 200pF
68p = 68pF
n39 = 390pF
6n8 = 6.8nF
20n = 20nF
10n = 10nF

Everything is right.

Crossposted from WoS Forums:

Hi there,
I've currently assembled another russian clone a "Compact 256 Turbo" from a PCB I bought. The machine appears to be fully functional and overall has a decent feature set. The machine seems to be largely inspired by either the KAY-256 or Scorpion 256.
Considering I already have a Pentagon 128 and the Scorpion 256 being the other "major" russian clone, I'm highly interested in fixing the Timing so I can watch Scorpion 256 Demos on the Compact 256. Timing seems to be largely compatible (69888 T-States per INT, 295/312 Lines on Screen, waitstates). Only problem I encountered is that the "start of paper" is about 8 lines off (12552 vs. 14344 if you want to reproduce them in UnrealSpeccy). You can see it on this simulated screenshot which perfectly matches up with the Compact (Top is Scorpion Timings, Bottom is Compact):
https://i.imgur.com/kPZVz1a.jpg

As you can see the Border gets drawn a bit too early (uppermost line is supposed to be red) resulting in a 8 Pixel offset between Border and Screen. Demo used is "Cool Suxx" by Flash Inc downloadable here: https://zxaaa.net/view_demo.php?id=5847
Other Scorpion Multicolor demos show similar problems.

Any ideas how to fix that? I've looked into the schematic and adapted how !INT is triggered, but with no change. Personally I'd love to understand how the Signals SS (related to Composite Sync I think), !KS, !BS, BK, !SCR relate how the video output is formed.

Documentation:
Schematic for Compact 128 here (that machine has a partially different schematic, but the very same problem): http://zxspectrum.it.omegahg.com/Com...OMPACT-128.pdf
PCB Top: https://cloud.mail.ru/public/Hzag/XQtJ8YHTJ
PCB Bottom: https://cloud.mail.ru/public/FPQA/XMBg7q5uS

- - - Updated - - -

Inverting !KS before going to the capacitor + RD gate slightly improved things. Now TestINT 1.10 is drawing the grey bar right between ZX/ZS and Pentagon Timings (previously it was under the ZX bar).

Found a solution that works :)
Вложение 72678

Final implementation on board:
Вложение 72695
Simplified Schematic:
Вложение 72696

Looking at the PCB layout I wonder if there's an easy way to implement reading of port #FF (fails in Test 4.30 and HFT 1.02).
The 2x 8 vias near the RAM ICs which have the D* and MD* buses seems to suggest it shouldn't be overly hard to add a small additional circuit for doing so.

I've found various implementations for various computers so far, but none exactly applicable for the compact yet.
What exactly is needed there? Of course a circuit that checks for the adress (8x AND) having the signals A0-A7, the /RD signal from the CPU (or better /IORD formed from /IOREQ and /RD?) and some timing/counter constant about which I'm unsure.

I'm aware adding port #FF adds very little to the machine and most games which require it have fixed versions around, but still it might be nice to have just in case.