Цитата:
CG10 are 0.8µm CMOS channelled gate arrays with dual columns. This means the whole structure is made of alternating transistor-filled and empty columns for routing. Each transistor column is made of many rows of two Basic Cells ("BC", a group of 4 transistors) set side by side.
For example, LSPC2-A2 uses the CG10103 master slice, which is one of the largest in the series. It has 21 columns and 291 rows of BC pairs, so 12222 BCs in total. Fujitsu gives a maximum of 11080 usable gates as an estimation for a real, functional design.
У нас фактически тоже самое. Тока фотки цветные)