Как-то так на Verilog, ispLever у меня скорее всего поломан.

module dc (high_addr_byte,nvram,dc1,dc2,rtc);

input [7:0] high_addr_byte;

output nvram,dc1,dc2,rtc;

assign nvram = (high_addr_byte >= 8'h80) && (high_addr_byte <= 8'hFC);
assign dc1 = ~ (high_addr_byte == 8'hFD);
assign dc2 = ~ (high_addr_byte == 8'hFE);
assign rtc = ~ (high_addr_byte == 8'hFF);

endmodule