Pentagon 48 или GRM1 начало INTа

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another static demo that draws into the border ...

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You can flash profi_rage_fix ROM image for this testing. on the link above. just wait a few seconds after running the demo.

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Or another static demo that draws into the border ...

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https://www.zxaaa.net/view_demos.php...&author=Author
https://www.zxaaa.net/view_demo.php?id=7367

Thanks zebest - that checkerboard picture is perfect for my purposes.
Using it I could verify that the border is "hanging" for ~3-8 pixels at the beginning of every line. Inverting !WRFE improves things but doesn't fully fix it yet.
Removing DD42 the offset persists, therefore I consider it safe to assume it's not due to the different muxing of the border/paper in the P48.
Вложение 67695

What's the actual purpose of VD14, C1 and R5?

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Using it I could verify that the border is "hanging" for ~3-8 pixels at the beginning of every line.

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Идеально было бы добиться такого результата, чтобы border и paper "расходились" не более чем на +\- 1 pixels (не 2, это целый такт, а именно 1 пиксель!)), совсем идеально на реальном Пентагон-е вряд ли получится. мое скромное мнение.

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What's the actual purpose of VD14, C1 and R5?

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It seems to me that these electronic parts are needed to delay the signal.

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Inverting !WRFE improves things but doesn't fully fix it yet.

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Inverting !WRFE must be on the wiring diagram, since writing to the register is carried out on the rising edge of the signal. Thanks for that test. I think I have the same problem in the computer Profi 5 with Pentagon Fix...

I think the computer is trying to piss me off ... I managed to pull this off - 1 Pixel off which I would consider almost perfect:
Вложение 67697

But ... after reset I was back to the "normal" 3-6 pixels depending whether I went with an inverted !WRFE or not (I actually have a switch for that for the moment).
This happened when I took A0 out of the circuit and instead went with inversions of the outputs of D9

Maybe the logic of VD1, VD2 and R8 is too slow? Can you check this schematic diagram?
Вложение 67698

Results in a total loss of sync (leaving out C8 I only get 2 'splits' instead of 3)
Вложение 67703

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Results in a total loss of sync (leaving out C8 I only get 2 'splits' instead of 3)

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Can you separate VD1 and VD2 from 9 pin DD14, connect 3 pin of 74LS32 to 9 pin DD14, unsolder R10 and R11 from C8 signal and 8 pin of DD14 and solder 14PIN_DD9 to R11?

This is how I modified the board:
Вложение 67707
Which would mean BLANK would still get generated by the diode-resistor OR-Gate

Checking further into the schematic I realized that the CPU has 2 gate delays less in the P128 (clocked by C20 [C25 in the P128 schematics]) than in the P48 (clocked by C20 going through 2 flip-flops becoming !CAS)