This is how I modified the board:
Which would mean BLANK would still get generated by the diode-resistor OR-Gate
Checking further into the schematic I realized that the CPU has 2 gate delays less in the P128 (clocked by C20 [C25 in the P128 schematics]) than in the P48 (clocked by C20 going through 2 flip-flops becoming !CAS)




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